1. Field of the Invention
The present invention relates to a solid state imaging device and a method of manufacturing the solid state imaging device.
2. Description of the Related Art
Referring to a solid state imaging device to be used in a digital camera, particularly, a solid state imaging device using a CCD (Charge Coupled Devices), it is necessary to suppress the generation of a smear to be a peculiar noise. In the case in which an object includes a light or sun having a high luminance, the smear easily appears. Actually, the noise seems to be whitish like a stripe or a band in upper and lower parts of a portion having a high luminance in an image which is picked up.
It is supposed that the smear appears by a mixture of a charge generated in a pixel portion having a high luminance in an imaging portion provided on the solid state imaging device into charges of other pixels which have been subjected to a photoelectric conversion and are being transferred. For a specific mechanism to generate the smear, four causes shown in (1) to (4) of FIG. 14 can be supposed. In other words, the smear is generated by at least one of the four causes in the following (1) to (4).
(1) A photoelectric conversion in a peripheral portion of a photodiode (PD): A light which is incident from an opening of a photodiode is not restricted to a component having a perpendicular incident angle to a surface. Moreover, the light has a property of a wave. For this reason, a light transmitted through the opening spreads and a photoelectric conversion is also carried out in a gate region provided on the periphery of the photodiode so that a charge corresponding to a noise is generated and mixed into a vertical charge transfer portion (VCCD).
(2) A diffusion current in a P-type region of an embedded photodiode: an electron generated in a P+ region is diffused over a surface of the embedded photodiode and is mixed into the vertical charge transfer portion (VCCD) in an adjacent column.
(3) A reflection and diffraction of a light incident from an opening portion of a shielding film (W or Al): an incident light is reflected or scattered at a boundary having a different refractive index, for example, a surface of a silicon substrate in an edge of the opening of the photodiode, and a charge is generated by the influence of the light and is mixed into the vertical charge transfer portion (VCCD).
(4) A transmission of the light through the shielding film (Al): If the shielding film (W or Al) which shields the vertical charge transfer portion (VCCD) has a defect, a light leaking out of the defect is incident on the vertical charge transfer portion to generate a charge so that a smear is generated.
In a recent solid state imaging device, however, the shielding is sufficiently carried out in many cases. For the actual cause of the smear, a diffusing component of a carrier subjected to the photoelectric conversion in (2) is dominant.
A current solid state imaging device of a CCD type is constituted by using an NMOS process as disclosed in JP-A-2005-209714, for example. More specifically, an electron having a high mobility is used as a carrier in the NMOS process. Therefore, a high speed operation can be carried out and the NMOS process is suitable for a device performance in the case in which a solid state imaging device is manufactured.
In the NMOS process, each circuit element is basically constituted by using an NMOS transistor having a structure shown in FIG. 15A. In FIG. 15A, an insulating layer 302 is formed on a surface of a substrate (a base material) 301 constituted by a P-type semiconductor (silicon), and a gate electrode 303 is formed on the insulating layer 302. Moreover, a source region 304 and a drain region 305 are constituted by an N-type semiconductor (silicon), respectively. Furthermore, in the example, N-type polysilicon (N-Poly) to be a general material is used as the gate electrode 303.
In other words, when a positive voltage is applied to the gate electrode 303 by a capacitor formed between the substrate 301 and the gate electrode 303, an electron is pulled toward a boundary surface between the substrate 301 and the insulating layer 302 so that an inverting layer (N type) is formed between the source region 304 and the drain region 305. A region (channel) having a high conductivity is formed between the source region 304 and the drain region 305 by the inverting layer, and the electron to be the carrier is moved therebetween. The movement of the electron can be controlled by the voltage to be applied to the gate electrode 303.
Referring to the NMOS transistor, it is necessary to employ a surface channel structure in order to reduce an interference (a short channel effect) generated when a distance between the source and the drain is short (2 μm or less). In the case in which it is necessary to reduce a threshold voltage, moreover, an electric potential distribution shown in FIG. 15B is generally formed by using N-type polysilicon as the gate electrode 303 in such a manner that a slight depletion state is generated even if the voltage to be applied to the gate electrode 303 is 0V, for example.
The related-art solid state imaging device of a CCD type using the NMOS process is constituted as shown in FIG. 16. FIG. 16 shows a sectional structure of an imaging cell corresponding to one pixel and a peripheral portion thereof. More specifically, in the imaging cell for generating signal charges corresponding to respective pixels, an N-type semiconductor region 402 provided in a P-type semiconductor region 401 constitutes a photodiode (PD). A P+ region 403 is formed on the N-type semiconductor region 402. Moreover, an N-type semiconductor region 404 for forming a vertical charge transfer portion (VCCD) to transfer the signal charge in a vertical direction is disposed on a side of the N-type semiconductor region 402. In order to transfer, to the vertical charge transfer portion, the signal charge generated and stored by the N-type semiconductor region 402 to be the photodiode, a gate electrode 406 is provided above the N-type semiconductor region 404. The gate electrode 406 and the N-type semiconductor region 404 are isolated from each other through an insulating layer 405. The gate electrode 406 is constituted by using N-type polysilicon (N-Poly) in the same manner as in a general NMOS transistor.
A two-dimensional solid state imaging device includes a large number of imaging cells which are arranged at a regular interval in directions of a row and a column. Therefore, another imaging cell is disposed in an adjacent position to one imaging cell. In the example shown in FIG. 16, an N-type semiconductor region 404(1) on a right side constitutes a vertical charge transfer portion in a column to which the imaging cell belongs, and an N-type semiconductor region 404(2) on a left side constitutes a vertical charge transfer portion belonging to another column which is adjacent to the imaging cell. Moreover, a gate electrode 406(1) is provided to transfer the signal charge from a photodiode of the imaging cell to the N-type semiconductor region 404(1) to be the vertical charge transfer portion in the column to which the imaging cell belongs, and a gate electrode 406(2) is provided to transfer the signal charge from a photodiode of the imaging cell belonging to the adjacent column to the N-type semiconductor region 404(2) of the column to which the imaging cell belongs. Moreover, the imaging cell and the imaging cell in the adjacent column are isolated from each other thorough the P+ region 403.
By the influence of a diffusion current in the P-type region (403) of the embedded photodiode, however, a part of the signal charges generated in the photodiode of the imaging cell are mixed into the vertical charge transfer portion (404(2)) belonging to the imaging cells in other adjacent columns in some cases. Consequently, the smear is caused. In other words, the signal charge leaks into the other adjacent columns through a path of (2) shown in FIG. 14.
In order to reduce the cause of the smear, in the related art, a surface shielding layer (corresponding to the P+ region 403 in FIG. 16) of the embedded photodiode is mainly shallowed as a countermeasure. When the surface shielding layer is excessively shallowed, however, it is impossible to obtain a structure of an embedded photodiode which is an original object. For this reason, there is a problem in that an interface generating current to cause a dark current or a white flaw is increased. Accordingly, the actual shallowness of the surface shielding layer is to be determined by a trade-off of the smear and the interface generating current.
In the related-art solid imaging device, a surface shielding layer is shallowed as a countermeasure for decreasing diffusing components of a carrier generated by a photoelectric conversion of a photodiode. Therefore, restrictions are imposed due to an increase in the interface generating current. Therefore, it is hard to effectively suppress a smear.
When the photodiode is exposed, moreover, the smear is generated. At this time, either a medium potential (VM) or a low potential (VL) is applied to a gate electrode for controlling an electric potential between the photodiode and the vertical charge transfer portion. When the medium potential (VM) is applied to the gate electrode so that the electric potential of the vertical charge transfer portion is reduced, the smear is generated.
By applying a negative bias as the medium potential (VM), accordingly, it is possible to form a potential barrier on an entrance of the vertical charge transfer portion. Therefore, it is possible to prevent the diffusing component of the carrier from flowing into the other adjacent columns, thereby suppressing the generation of the smear.
In the case of the solid state imaging device to be particularly used in a household product, however, it is necessary to reduce a consumed power and to decrease the number of power supplies. Under the actual circumstances, therefore, a ground potential (GND) is to be applied as the medium potential (VM) to the gate electrode. For this reason, the negative bias cannot be applied as the medium potential (VM) in the related-art solid state imaging device so that the potential barrier cannot be formed on the entrance of the vertical charge transfer portion.